With the continuous development of semiconductor technology, dimensions of semiconductor devices continue to decrease. With the reduction of the dimensions of the semiconductor devices, the impact of contact resistance of Metal-Oxide-Semiconductor (MOS) transistors on the performance of the MOS transistors and the performance of the entire semiconductor chip is gradually increasing. To improve the performance of the semiconductor chip, the contact resistance of the MOS transistors needs to be reduced. With the reduction of the dimensions of the semiconductor devices, the areas of the source region and the drain region become smaller and smaller. Therefore, the contact resistance between the source region, the drain region and the metal plug increases with the decreasing of the dimension of the semiconductor device. The large contact resistance between the source region, the drain region and the metal plug affects the performance of the MOS transistor and limits the operation speed of the semiconductor device.
Self-aligned silicide (Salicide) formed on the source region and the drain region can effectively reduce the contact resistance between the source region, the drain region and the metal plug. Currently, the process for forming the self-aligned silicide often includes: forming a metal layer on the silicon layer by an evaporation process or a sputtering process; performing an annealing process, such that the metal and silicon can react to form metal silicide; and removing the metal layer not reacted with the silicon.
In addition, to improve the operation speed of the chip and to improve the performance of the MOS transistor, the mobility of carriers in the channel is improved by introducing a stress layer in the source region and the drain region of the MOS transistor. The source region and the drain region of the MOS transistor made of germanium silicon material or carbon silicon material can introduce compressive stress or tensile stress in the channel region of the MOS transistor, thus improving the performance of the MOS transistor.
However, with the reduction of the dimensions of the semiconductor devices, the dimensions of the MOS transistors also decrease accordingly, it is more difficult to form the self-aligned silicide, resulting in the decreasing of the performance of the MOS transistors. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.